SoC Partition Design Owner Job - (folsom, california)
SoC Partition Design Owner :
Description Group Specific Description In this position, you will be responsible for the design and implementation of partition level hierarchies (Synthesis, Place and Route and Convergence) for the next generation of Intels SoC client products.
You will be part of a team that will work with Front End RTL and FC SoC Integration teams developing leading edge CPU products on the next generation process technology.
Responsibilities will include, but are not limited to:
Work within a team of partition design owners and SD leads to implement Client CPU SoC products.
Work cross:
geo with stakeholders that may own RTL, FC integration and product convergence.
Personal responsibility for the implementation of partitions from Synthesis to APR, timing and layout completion, including complete convergence of backend design to all quality criteria.
Work with uArch and logic teams to implement late design changes to meet product LZs and bug closure.
Ensure all product goals are met for the design owned.
Qualifications You should possess a Masters degree or a minimum of a Bachelor degree in Electrical Engineering with equivalent experience.
Minimum Requirements:
5
years combined experience of working in/around ASIC or Microprocessor design groups either as a synthesis design owner or synthesis methodology/tool developer.
5
years experience with synthesis tools, auto place and route, and static timing analysis.
5
years experience with floorplanning, clock tree synthesis, and layout closure is a must.
You should have strong communication, organizational and time management skills.
Strong initiative, ability to handle ambiguity and discipline to follow:
through is required.
Preferred Requirements:
Understanding of RTL coding, basic logic design and power optimization are highly desired Job Category:
Engineering Full/Part Time:
Full Time Job Type:
Experienced Regular/Temporary:
Regular Posting Date:
Apr 3, 2014 Apply Before :
Apr 3, 2015 Business Group The Platform Engineering Group (PEG) is responsible for the design, development, and production of system:
on:
a:
chip (SoC) products that go into Intel's next generation client and mobile platforms.
PEG strives to lead the industry moving forward through product innovation and world class engineering.
Source:
http:
//www.
tiptopjob.
com/jobs/28519201_job.
asp?source=trovit.
Estimated Salary: $20 to $28 per hour based on qualifications.
Description Group Specific Description In this position, you will be responsible for the design and implementation of partition level hierarchies (Synthesis, Place and Route and Convergence) for the next generation of Intels SoC client products.
You will be part of a team that will work with Front End RTL and FC SoC Integration teams developing leading edge CPU products on the next generation process technology.
Responsibilities will include, but are not limited to:
Work within a team of partition design owners and SD leads to implement Client CPU SoC products.
Work cross:
geo with stakeholders that may own RTL, FC integration and product convergence.
Personal responsibility for the implementation of partitions from Synthesis to APR, timing and layout completion, including complete convergence of backend design to all quality criteria.
Work with uArch and logic teams to implement late design changes to meet product LZs and bug closure.
Ensure all product goals are met for the design owned.
Qualifications You should possess a Masters degree or a minimum of a Bachelor degree in Electrical Engineering with equivalent experience.
Minimum Requirements:
5
years combined experience of working in/around ASIC or Microprocessor design groups either as a synthesis design owner or synthesis methodology/tool developer.
5
years experience with synthesis tools, auto place and route, and static timing analysis.
5
years experience with floorplanning, clock tree synthesis, and layout closure is a must.
You should have strong communication, organizational and time management skills.
Strong initiative, ability to handle ambiguity and discipline to follow:
through is required.
Preferred Requirements:
Understanding of RTL coding, basic logic design and power optimization are highly desired Job Category:
Engineering Full/Part Time:
Full Time Job Type:
Experienced Regular/Temporary:
Regular Posting Date:
Apr 3, 2014 Apply Before :
Apr 3, 2015 Business Group The Platform Engineering Group (PEG) is responsible for the design, development, and production of system:
on:
a:
chip (SoC) products that go into Intel's next generation client and mobile platforms.
PEG strives to lead the industry moving forward through product innovation and world class engineering.
Source:
http:
//www.
tiptopjob.
com/jobs/28519201_job.
asp?source=trovit.
Estimated Salary: $20 to $28 per hour based on qualifications.
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