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PDG Full Chip Layout Verification DA CG 2014 Job - (folsom, california) PDG Full Chip Layout Verification DA CG 2014 : Description Come join Intels Product Development Group (PDG) as a Full Chip Layout Verification/Tapein DA. In this position you will be developing, deploying, and supporting Section and Full:chip Layout Verification tools and methodologies in support of cutting:edge Client CPU projects within CMPG. This includes: : Support for Section and Full:chip Layout Verification flows and in the UE/PDS environment, including occasional cross:site support :. After registering you may be able to apply for this job directly (if still active) on ((None))'s site. Future job matches may be sent from Geebo approved job partners.
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